document number: 91 299 www.vishay.com s11-0518-rev. b, 21-mar-11 1 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet irl530, SIHL530 vishay siliconix features ? dynamic dv/dt rating ? repetitive avalanche rated ? logic-level gate drive ?r ds(on) specified at v gs = 4 v and 5 v ? 175 c operating temperature ?fast switching ? ease of paralleling ? compliant to rohs directive 2002/95/ec description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost effectiveness. the to-220ab package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 w. the low thermal resistance and low package cost of the to-220ab contribute to its wide acceptance thro ughout the industry. notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 1.9 mh, r g = 25 i as = 15 a (see fig. 12). c. i sd 15 a, di/dt 140 a/ s, v dd v ds , t j 175 c. d. 1.6 mm from case. product summary v ds (v) 100 r ds(on) ( )v gs = 5.0 v 0.16 q g (max.) (nc) 28 q gs (nc) 3.8 q gd (nc) 14 configuration single n-channel mosfet g d s to-220ab g d s available rohs* compliant ordering information package to-220ab lead (pb)-free irl530pbf SIHL530-e3 snpb irl530 SIHL530 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 100 v gate-source voltage v gs 10 continuous drain current v gs at 5.0 v t c = 25 c i d 15 a t c = 100 c 11 pulsed drain current a i dm 60 linear derating factor 0.59 w/c single pulse avalanche energy b e as 290 mj repetitive avalanche current a i ar 15 a repetitive avalanche energy a e ar 8.8 mj maximum power dissipation t c = 25 c p d 88 w peak diode recovery dv/dt c dv/dt 5.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 175 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91299 2 s11-0518-rev. b, 21-mar-11 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix notes a. repetitive rating; pulse widt h limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w case-to-sink, flat, greased surface r thcs 0.50 - maximum junction-to-case (drain) r thjc -1.7 specifications (t j = 25 c, unless otherwise noted) parameter symbol test cond itions min. typ. max. unit static drain-source brea kdown voltage v ds v gs = 0 v, i d = 250 a 100 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.14 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.0 - 2.0 v gate-source leakage i gss v gs = 10 - - 100 na zero gate voltage drain current i dss v ds = 100 v, v gs = 0 v - - 25 a v ds = 80 v, v gs = 0 v, t j = 150 c - - 250 drain-source on-state resistance r ds(on) v gs = 5.0 v i d = 9.0 a b --0.16 v gs = 4.0 v i d = 7.5 a b --0.22 forward transconductance g fs v ds = 50 v, i d = 9.0 a b 6.4 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 930 - pf output capacitance c oss - 250 - reverse transfer capacitance c rss -57- total gate charge q g v gs = 5.0 v i d = 15 a, v ds = 80 v, see fig. 6 and 13 b --28 nc gate-source charge q gs --3.8 gate-drain charge q gd --14 turn-on delay time t d(on) v dd = 50 v, i d = 15 a, r g = 12 , r d = 32 , see fig. 10 b -4.7- ns rise time t r - 100 - turn-off delay time t d(off) -22- fall time t f -48- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol showing the integral reverse p - n junction diode --15 a pulsed diode forward current a i sm --60 body diode voltage v sd t j = 25 c, i s = 15 a, v gs = 0 v b --2.5 v body diode reverse recovery time t rr t j = 25 c, i f = 15 a, di/dt = 100 a/s b - 150 200 ns body diode reverse recovery charge q rr -0.931.4 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91 299 www.vishay.com s11-0518-rev. b, 21-mar-11 3 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 175 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
www.vishay.com document number: 91299 4 s11-0518-rev. b, 21-mar-11 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
document number: 91 299 www.vishay.com s11-0518-rev. b, 21-mar-11 5 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 5 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f
www.vishay.com document number: 91299 6 s11-0518-rev. b, 21-mar-11 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd 5 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 5.0 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
document number: 91 299 www.vishay.com s11-0518-rev. b, 21-mar-11 7 this datasheet is subject to change without notice. the product described here in and this datasheet are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 irl530, SIHL530 vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldw ide manufacturing capability. prod ucts may be manufactured at on e of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents su ch as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91299 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
package information www.vishay.com vishay siliconix revison: 02-nov-15 1 document number: 66542 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-220-1 note ? m* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for hvm m * 3 2 1 l l(1) d h(1) q ? p a f j(1) b(1) e(1) e e b c dim. millimeters inches min. max. min. max. a 4.14 4.70 0.163 0.185 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 d 14.32 15.86 0.564 0.624 e 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 f 0.51 1.40 0.020 0.055 h(1) 6.10 6.70 0.240 0.264 j(1) 2.41 2.92 0.095 0.115 l 13.36 14.40 0.526 0.567 l(1) 3.33 4.05 0.131 0.159 ? p 3.53 3.94 0.139 0.155 q 2.54 3.00 0.100 0.118 ecn: x15-0339-rev. b, 02-nov-15 dwg: 6031
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